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general description the max1471 low-power, cmos, superheterodyne, rf dual-channel receiver is designed to receive both ampli- tude-shift-keyed (ask) and frequency-shift-keyed (fsk) data without reconfiguring the device or introducing any time delay normally associated with changing modula- tion schemes. the max1471 requires few external com- ponents to realize a complete wireless rf digital data receiver for the 300mhz to 450mhz ism bands. the max1471 includes all the active components required in a superheterodyne receiver including: a low- noise amplifier (lna), an image-reject (ir) mixer, a fully integrated phase-locked loop (pll), local oscillator (lo), 10.7mhz if limiting amplifier with received-signal- strength indicator (rssi), low-noise fm demodulator, and a 3v voltage regulator. differential peak-detecting data demodulators are included for both the fsk and ask analog baseband data recovery. the max1471 includes a discontinuous receive (drx) mode for low- power operation, which is configured through a serial interface bus. the max1471 is available in a 32-pin thin qfn package and is specified over the automotive -40? to +125? temperature range. applications automotive remote keyless entry (rke) tire pressure monitoring systems garage door openers wireless sensors wireless keys security systems medical systems home automation local telemetry systems features ask and fsk demodulated data on separate outputs specified over automotive -40c to +125c temperature range low operating supply voltage down to 2.4v on-chip 3v regulator for 5v operation low operating supply current 7ma continuous receive mode 1.1 a deep-sleep mode discontinuous receive (drx) low-power management fast-on startup feature < 250 s integrated pll, vco, and loop filter 45db integrated image rejection rf input sensitivity* ask: -114dbm fsk: -108dbm selectable if bw with external filter programmable through serial user interface rssi output and high dynamic range with agc max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver ________________________________________________________________ maxim integrated products 1 32 + 31 30 29 28 27 26 9 101112131415 18 19 20 21 22 23 24 7 6 5 4 3 2 1 max1471 thin qfn top view dsa+ dsa- opa+ dfa xtal2 xtal1 avdd 8 lnain pdmaxa pdmina ada ta hvin sclk dio 25 fdata dvdd dgnd dff opf+ dsf+ dsf- pdmaxf 17 pdminf ifin- agnd 16 ifin+ mixout mixin- mixin+ lnaout lnasrc cs pin configuration 19-3272; rev 3; 12/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * 0.2% ber, 4kbps, manchester-encoded data, 280khz if bw ordering information part temp range pin-package max1471atj/v+ -40 c to +125 c 32 thin qfn-ep** + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. ** ep = exposed pad.
max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. high-voltage supply, hvin to dgnd ......................-0.3v, +6.0v low-voltage supply, avdd and dvdd to agnd ....-0.3v, +4.0v sclk, dio, cs , adata, fdata ...................................(dgnd - 0.3v) to (hvin + 0.3v) all other pins............................(agnd - 0.3v) to (avdd + 0.3v) continuous power dissipation (t a = +70?) 32-pin thin qfn (derate 21.3mw/? above +70 ?) ...1702mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) ................................ +300? soldering temperature (reflow) ...................................... +260? dc electrical characteristics ( typical application circuit , v avdd = v dvdd = v hvin = +2.4v to +3.6v, f rf = 300mhz to 450mhz, t a = -40? to +125?, unless other- wise noted. typical values are at v avdd = v dvdd = v hvin = +3.0v, f rf = 434 mhz, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units general characteristics supply voltage (5v) hvin avdd and dvdd unconnected from hvin, but connected together 4.5 5.0 5.5 v supply voltage (3v) v dd hvin, avdd, and dvdd connected to power supply 2.4 3.0 3.6 v operating 7.0 8.4 ma polling duty cycle: 10% duty cycle 705 855 drx mode off current 5.0 14.2 t a < +85? deep-sleep current 1.1 7.1 ? operating 8.5 ma polling duty cycle: 10% duty cycle 865 drx mode off current 15.5 t a < +105? (note 2) deep-sleep current 13.4 ? operating 8.6 ma polling duty cycle: 10% duty cycle 900 drx mode off current 44.1 supply current i dd t a < +125? (note 2) deep-sleep current 36.4 ? startup time t on time for final signal detection, does not include baseband filter settling (note 2) 200 250 ? digital outputs (dio, adata, fdata) output high voltage v oh i source = 250? (note 2) v hvin - 0.15 v output low voltage v ol i sink = 250? (note 2) 0.15 v digital inputs ( cs , dio, sclk) input high threshold v ih 0.9 x v hvin v input low threshold v il . 0.1 x v hvin v
max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver _______________________________________________________________________________________ 3 dc electrical characteristics (continued) ( typical application circuit , v avdd = v dvdd = v hvin = +2.4v to +3.6v, f rf = 300mhz to 450mhz, t a = -40? to +125?, unless other- wise noted. typical values are at v avdd = v dvdd = v hvin = +3.0v, f rf = 434 mhz, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units input-high leakage current i ih (note 2) -20 ? input-low leakage current i il (note 2) 20 ? input capacitance c in (note 2) 2.0 pf voltage regulator output voltage v reg v hvin = 5.0v, i load = 7.0ma 3.0 v ac electrical characteristics ( typical application circuit , v avdd = v dvdd = v hvin = +2.4v to +3.6v, f rf = 300mhz to 450mhz, t a = -40? to +125?, unless other- wise noted. typical values are at v avdd = v dvdd = v hvin = +3.0v, f rf = 434 mhz, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units general characteristics ask -114 receiver sensitivity rf in 0.2% ber, 4kbps manchester code, 280khz if bw, 50 ? fsk -108 dbm maximum receiver input power level rf max 0 dbm receiver input frequency range f rf 300 450 mhz receiver image rejection ir (note 3) 45 db lna/mixer (note 4) f rf = 315mhz 1 - j4.7 lna input impedance z in_lna normalized to 50 ? = ( ) () ( ) () ? if input impedance z in_if 330 ? operating frequency f if 10.7 mhz 3db bandwidth 10 mhz fm demodulator demodulator gain g fm 2.2 mv/khz
max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver 4 _______________________________________________________________________________________ ac electrical characteristics (continued) ( typical application circuit , v avdd = v dvdd = v hvin = +2.4v to +3.6v, f rf = 300mhz to 450mhz, t a = -40? to +125?, unless other- wise noted. typical values are at v avdd = v dvdd = v hvin = +3.0v, f rf = 434 mhz, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units analog baseband maximum data filter bandwidth bw df 50 khz maximum data slicer bandwidth bw ds 100 khz maximum peak detector bandwidth bw pd 50 khz manchester coded 33 maximum data rate nonreturn to zero (nrz) 66 kbps crystal oscillator crystal frequency f xtal 9.04 13.728 mhz frequency pulling by v dd 3 ppm/v crystal load capacitance 3pf digital interface timing (see figure 8) minimum sclk setup to falling edge of cs t sc 30 ns minimum cs falling edge to sclk rising-edge setup time t css 30 ns minimum cs idle time t csi 125 ns minimum cs period t cs 2.125 ? maximum sclk falling edge to data valid delay t do 80 ns minimum data valid to sclk rising-edge setup time t ds 30 ns minimum data valid to sclk rising-edge hold time t dh 30 ns minimum sclk high pulse width t ch 100 ns minimum sclk low pulse width t cl 100 ns minimum cs rising edge to sclk rising-edge hold time t csh 30 ns maximum cs falling edge to output enable time t dv 25 ns maximum cs rising edge to output disable time t tr 25 ns note 1: production tested at t a = +85?. guaranteed by design and characterization over entire temperature range. note 2: guaranteed by design and characterization. not production tested. note 3: the oscillator register (0x3) is set to the nearest integer result of f xtal / 100khz (see the oscillator frequency register section). note 4: input impedance is measured at the lnain pin. note that the impedance at 315mhz includes the 15nh inductive degeneration from the lna source to ground. the impedance at 434mhz includes a 10nh inductive degeneration connected from the lna source to ground. the equivalent input circuit is 50 ? in series with 2.2pf. the voltage conversion gain is measured with the lna input matching inductor, the degeneration inductor, and the lna/mixer resonator in place, and does not include the if fil- ter insertion loss.
max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver _______________________________________________________________________________________ 5 6.0 6.4 6.8 7.2 7.6 8.0 2.4 2.7 3.0 3.3 3.6 supply current vs. supply voltage max1471 toc01 supply voltage (v) supply current (ma) +125 c +105 c +85 c +25 c -40 c 6.0 6.6 6.4 6.2 6.8 7.0 7.2 7.4 7.6 7.8 8.0 300 325 375 350 400 425 450 supply current vs. rf frequency max1471 toc02 rf frequency (mhz) supply current (ma) +125 c -40 c +25 c +105 c +85 c 0 2 6 4 10 8 12 -40 10 -15 35 60 85 110 deep-sleep current vs. temperature max1471 toc03 temperature ( c) deep-sleep current ( a) 100 10 1 0.1 0.01 -123 -121 -119 -117 -115 -113 -111 bit-error rate vs. average input power (ask data) max1471 toc04 average input power (dbm) bit-error rate (%) 0.2% ber f rf = 434mhz f rf = 315mhz 280khz if bw 100 10 1 0.1 0.01 -115 -110 -113 -108 -105 bit-error rate vs. average input power (fsk data) max1471 toc05 average input power (dbm) bit-error rate 0.2% ber f rf = 434mhz f rf = 315mhz 280khz if bw frequency deviation = 50khz -120 -117 -111 -114 -105 -108 -102 -40 10 -15 35 60 85 110 sensitivity vs. temperature (ask data) max1471 toc06 temperature ( c) sensitivity (dbm) 280khz if bw 0.2% ber f rf = 434mhz f rf = 315mhz -112 -110 -106 -108 -104 -102 -40 10 -15 35 60 85 110 sensitivity vs. temperature (fsk data) max1471 toc07 temperature ( c) sensitivity (dbm) 280khz if bw 0.2% ber f rf = 434mhz f rf = 315mhz frequency deviation = 50khz -98 -112 110100 sensitivity vs. frequency deviation (fsk data) -108 -110 max1471 toc08 frequency deviation (khz) sensitivity (dbm) -106 -102 -104 -100 280khz if bw 0.2% ber rssi vs. rf input power max1471 toc09 0 0.2 0.6 0.4 1.2 1.4 1.0 0.8 1.6 rssi (v) -130 -90 -70 -110 -50 -30 -10 10 rf input power (dbm) agc hysteresis: 3db high-gain mode low-gain mode agc switch point typical operating characteristics ( typical application circuit , v avdd = v dvdd = v hvin = +3.0v, f rf = 434mhz, t a = +25?, unless otherwise noted.)
max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver 6 _______________________________________________________________________________________ 0 0.6 0.3 1.2 0.9 1.8 1.5 2.1 -90 -50 -70 -30 -10 10 rssi and delta vs. if input power max1471 toc10 rf input power (dbm) rssi (v) -3.5 -1.5 -2.5 0.5 -0.5 2.5 1.5 3.5 delta (%) rssi delta 0 0.4 0.8 1.2 1.6 2.0 10.4 10.5 10.7 10.6 10.8 10.9 11.0 fsk demodulator output vs. if frequency max1471 toc11 if frequency (mhz) fsk demodulator output (v) -10 10 0 30 20 50 40 60 01015 5 202530 system voltage gain vs. if frequency max1471 toc12 if frequency (mhz) system gain (db) 45db image rejection upper sideband lower sideband from rfin to mixout f rf = 434mhz 38 40 44 42 46 48 -40 10 -15 35 60 85 110 image rejection vs. temperature max1471 toc13 temperature ( c) image rejection (db) f rf = 315mhz f rf = 434mhz 5 -20 110100 normalized if gain vs. if frequency -15 max1471 toc14 if frequency (mhz) normalized if gain (dbm) -10 -5 0 10db/ div start: 50mhz stop: 1ghz s11 log-magnitude plot with matching network of rfin (434mhz) max1471 toc15 0db 0db 434mhz -16.4db s11 smith chart of rfin (434mhz) max1471 toc16 500mhz 200mhz typical operating characteristics (continued) ( typical application circuit , v avdd = v dvdd = v hvin = +3.0v, f rf = 434mhz, t a = +25?, unless otherwise noted.)
max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver _______________________________________________________________________________________ 7 input impedance vs. inductive degeneration max1471 toc17 inductive degeneration (nh) real impedance ( ? ) 10 10 20 30 40 50 60 70 80 90 0 1 100 f rf = 315mhz l1 = 0nh imaginary impedance real impedance -325 -300 -275 -250 -225 -200 -175 -150 -125 -350 imaginary impedance ( ? ) input impedance vs. inductive degeneration max1471 toc18 inductive degeneration (nh) real impedance ( ? ) 10 10 20 30 40 50 60 70 80 90 0 1 100 f rf = 434mhz l1 = 0nh imaginary impedance -325 -300 -275 -250 -225 -200 -175 -150 -125 -350 imaginary impedance ( ? ) real impedance -50 -120 100 1k 1m 10m phase noise vs. offset frequency -110 -90 -100 -60 -70 -80 max1471 toc19 offset frequency (hz) phase noise (dbc/hz) 10k 100k f rf = 315mhz -50 -120 100 1k 1m 10m phase noise vs. offset frequency -110 -90 -100 -60 -70 -80 max1471 toc20 offset frequency (hz) phase noise (dbc/hz) 10k 100k f rf = 434mhz typical operating characteristics (continued) ( typical application circuit , v avdd = v dvdd = v hvin = +3.0v, f rf = 434mhz, t a = +25?, unless otherwise noted.) pin name function 1 dsa- inverting data slicer input for ask data 2 dsa+ noninverting data slicer input for ask data 3 opa+ noninverting op-amp input for the ask sallen-key data filter 4 dfa data-filter feedback node. input for the feedback of the ask sallen-key data filter. 5 xtal2 2nd crystal input pin description
max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver 8 _______________________________________________________________________________________ pin name function 6 xtal1 1st crystal input 7 avdd analog power-supply voltage for rf sections. avdd is connected to an on-chip +3.0v low-dropout regulator. decouple to agnd with a 0.1? capacitor. 8 lnain low-noise amplifier input 9 lnasrc low-noise amplifier source for external inductive degeneration. connect an inductor to agnd to set lna input impedance. 10 lnaout low-noise amplifier output. connect to mixer through an lc tank filter. 11 mixin+ differential mixer input. must be ac-coupled to driving input. 12 mixin- differential mixer input. bypass to agnd with a capacitor. 13 mixout 330 ? mixer output. connect to the input of the 10.7mhz if filter. 14 agnd analog ground 15 ifin- differential 330 ? if limiter amplifier input. bypass to agnd with a capacitor. 16 ifin+ differential 330 ? if limiter amplifier input. connect to output of the 10.7mhz if filter. 17 pdminf minimum-level peak detector for fsk data 18 pdmaxf maximum-level peak detector for fsk data 19 dsf- inverting data slicer input for fsk data 20 dsf+ noninverting data slicer input for fsk data 21 opf+ noninverting op-amp input for the fsk sallen-key data filter 22 dff data-filter feedback node. input for the feedback of the fsk sallen-key data filter. 23 dgnd digital ground 24 dvdd digital power-supply voltage for digital sections. connect to avdd. decouple to dgnd with a 10nf capacitor. 25 fdata digital baseband fsk demodulator data output 26 cs active-low chip-select input 27 dio serial data input/output 28 sclk serial interface clock input 29 hvin high-voltage supply input. for 3v operation, connect hvin to avdd and dvdd. 30 adata digital baseband ask demod data output 31 pdmina minimum-level peak detector for ask output 32 pdmaxa maximum-level peak detector for ask output ep exposed pad. connect to ground. pin description (continued)
max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver _______________________________________________________________________________________ 9 fsk demodulator rssi 90 0 vco divide by 32 phase detector crystal oscillator serial interface, control registers, and polling timer loop filter lna 3.0v reg 3.0v 4 dfa 3 opa+ 2 dsa+ 31 pdmina 32 pdmaxa 1 dsa- 30 adata 8 lnain 9 lnasrc 6 xtal1 14 agnd 5 xtal2 26 27 dio 28 sclk 24 23 dgnd 29 hvin avdd 7 10 lnaout 11 mixin+ 12 mixin- 13 mixout 15 ifin- 16 ifin+ 25 fdata 19 dsf- 18 pdmaxf 17 pdminf 20 dsf+ 21 opf+ 22 dff dvdd cs if limiting amps ask data filter fsk data filter image rejection ask fsk r df1 100k ? r df2 100k ? r df1 100k ? r df2 100k ? max1471 functional diagram
max1471 detailed description the max1471 cmos superheterodyne receiver and a few external components provide a complete ask/fsk receive chain from the antenna to the digital output data. depending on signal power and component selection, data rates as high as 33kbps using manchester code (66kbps nonreturn to zero) can be achieved. the max1471 is designed to receive binary fsk or ask data on a 300mhz to 450mhz carrier. ask modu- lation uses a difference in amplitude of the carrier to represent logic 0 and logic 1 data. fsk uses the differ- ence in frequency of the carrier to represent a logic 0 and logic 1. low-noise amplifier (lna) the lna is a cascode amplifier with off-chip inductive degeneration that achieves approximately 28db of volt- age gain that is dependent on both the antenna-match- ing network at the lna input, and the lc tank network between the lna output and the mixer inputs. the off-chip inductive degeneration is achieved by con- necting an inductor from lnasrc to agnd. this induc- tor sets the real part of the input impedance at lnain, allowing for a flexible match to low input impedances such as a pcb trace antenna. a nominal value for this inductor with a 50 ? input impedance is 15nh at 315mhz and 10nh at 434mhz, but the inductance is affected by pcb trace length. see the typical operating characteristics to see the relationship between the inductance and input impedance. the inductor can be shorted to ground to increase sensitivi- ty by approximately 1db, but the input match is not optimized for 50 ? . the lc tank filter connected to lnaout comprises l2 and c9 (see the typical application circuit ). select l2 and c9 to resonate at the desired rf input frequency. the resonant frequency is given by: where l total = l2 + l parasitics and c total = c9 + c parasitics . l parasitics and c parasitics include inductance and capacitance of the pcb traces, package pins, mixer input impedance, lna output impedance, etc. these parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center fre- quency. lab experimentation should be done to opti- mize the center frequency of the tank. automatic gain control (agc) when the agc is enabled, it monitors the rssi output. when the rssi output reaches 1.28v, which corre- sponds to an rf input level of approximately -64dbm, the agc switches on the lna gain reduction attenuator. the attenuator reduces the lna gain by 35db, thereby reducing the rssi output by about 0.55v. the lna resumes high-gain mode when the rssi output level drops back below 0.68v (approximately -67dbm at the rf input) for a programmable interval called the agc dwell time. the agc has a hysteresis of approximately 3db. with the agc function, the rssi dynamic range is increased, allowing the max1471 to reliably produce an ask output for rf input levels up to 0dbm with a modu- lation depth of 18db. agc is not necessary and can be disabled when utilizing only the fsk data path. the max1471 features an agc lock controlled by the agc lock bit (see table 8). when the bit is set, the lna is locked in its present gain state. mixer a unique feature of the max1471 is the integrated image rejection of the mixer. this device was designed to eliminate the need for a costly front-end saw filter for many applications. the advantage of not using a saw filter is increased sensitivity, simplified antenna match- ing, less board space, and lower cost. the mixer cell is a pair of double-balanced mixers that perform an iq downconversion of the rf input to the 10.7mhz intermediate frequency (if) with low-side injection (i.e., f lo = f rf - f if ). the image-rejection circuit then combines these signals to achieve approximately 45db of image rejection. low-side injection is required as high-side injection is not possible due to the on-chip image rejection. the if output is driven by a source fol- lower, biased to create a driving impedance of 330 ? to interface with an off-chip 330 ? ceramic if filter. the voltage conversion gain driving a 330 ? load is approxi- mately 19.5db. note that the mixin+ and mixin- inputs are functionally identical. phase-locked loop (pll) the pll block contains a phase detector, charge pump/integrated loop filter, voltage-controlled oscillator (vco), asynchronous 32x clock divider, and crystal oscillator. this pll does not require any external com- ponents. the relationship between the rf, if, and refer- ence frequencies is given by: f ref = (f rf - f if )/32 to allow the smallest possible if bandwidth (for best sen- sitivity), the tolerance of the reference must be minimized. f lc total total = 1 2 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver 10 ______________________________________________________________________________________
intermediate frequency (if) the if section presents a differential 330 ? load to pro- vide matching for the off-chip ceramic filter. it contains five ac-coupled limiting amplifiers with a bandpass-fil- ter-type response centered near the 10.7mhz if fre- quency with a 3db bandwidth of approximately 10mhz. for ask data, the rssi circuit demodulates the if to baseband by producing a dc output proportional to the log of the if signal level with a slope of approxi- mately 16mv/db. for fsk, the limiter output is fed into a pll to demodulate the if. fsk demodulator the fsk demodulator uses an integrated 10.7mhz pll that tracks the input rf modulation and determines the difference between frequencies as logic-level ones and zeros. the pll is illustrated in figure 1. the input to the pll comes from the output of the if limiting amplifiers. the pll control voltage responds to changes in the fre- quency of the input signal with a nominal gain of 2.2mv/khz. for example, an fsk peak-to-peak devia- tion of 50khz generates a 110mv p-p signal on the con- trol line. this control line is then filtered and sliced by the fsk baseband circuitry. the fsk demodulator pll requires calibration to over- come variations in process, voltage, and temperature. for more information on calibrating the fsk demodula- tor, see the calibration section. the maximum calibra- tion time is 120?. in drx mode, the fsk demodulator calibration occurs automatically just before the ic enters sleep mode. crystal oscillator the xtal oscillator in the max1471 is used to generate the local oscillator (lo) for mixing with the received sig- nal. the xtal oscillator frequency sets the received signal frequency as: f receive = (f xtal x 32) +10.7mhz the received image frequency at: f image = (f xtal x 32) -10.7mhz is suppressed by the integrated quadrature image- rejection circuitry. for an input rf frequency of 315mhz, a reference fre- quency of 9.509mhz is needed for a 10.7mhz if fre- quency (low-side injection is required). for an input rf frequency of 433.92mhz, a reference frequency of 13.2256mhz is required. the xtal oscillator in the max1471 is designed to pre- sent a capacitance of approximately 3pf between the xtal1 and xtal2. if a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, intro- ducing an error in the reference frequency. crystals designed to operate with higher differential load capac- itance always pull the reference frequency higher. in actuality, the oscillator pulls every crystal. the crys- tal? natural frequency is really below its specified fre- quency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. this pulling is already accounted for in the specification of the load capacitance. additional pulling can be calculated if the electrical parameters of the crystal are known. the frequency pulling is given by: where: f p is the amount the crystal frequency pulled in ppm. c m is the motional capacitance of the crystal. c case is the case capacitance. c spec is the specified load capacitance. c load is the actual load capacitance. when the crystal is loaded as specified, i.e., c load = c spec , the frequency pulling equals zero. f c cccc p m case load case spec 6 = + ? + ? ? ? ? ? ? 2 11 10 max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver ______________________________________________________________________________________ 11 figure 1. fsk demodulator pll block diagram loop filter 10.7mhz vco 2.2mv/khz charge pump phase detector if limiting amps to fsk baseband filter and data slicer
max1471 data filters the data filters for the ask and fsk data are imple- mented as a 2nd-order lowpass sallen-key filter. the pole locations are set by the combination of two on- chip resistors and two external capacitors. adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. the cor- ner frequency in khz should be set to approximately 1.5 times the fastest expected manchester data rate in kbps from the transmitter. keeping the corner frequen- cy near the data rate rejects any noise at higher fre- quencies, resulting in an increase in receiver sensitivity. the configuration shown in figure 3 can create a butterworth or bessel response. the butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40db/decade for the two-pole filter. the bessel filter has a linear phase response, which works well for filtering digital data. to calculate the value of the capacitors, use the following equations, along with the coefficients in table 2: where f c is the desired 3db corner frequency. for example, choose a butterworth filter response with a corner frequency of 5khz: c b akf c a kf f1 c f2 c = ()()() = ()()() 100 4 100 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver 12 ______________________________________________________________________________________ figure 2. typical application circuit ask data out sclk dio fsk data out max1471 v cc in gnd y2 out cs dff 22 dsf- 19 pdmaxf 18 pdminf 17 pdmaxa 32 pdmina 31 adata 30 hvin 29 slck 28 dio 27 26 fdata 25 dsa+ 2 lnasrc 9 lnaout 10 mixout 13 agnd 14 ifin+ 16 cs dvdd 24 dgnd 23 c23 v dd opf+ 21 c21 c22 r8 c27 dsf+ 20 v dd opa+ 3 c3 opf+ 21 c21 dsa- 1 c5 dfa 4 r3 c4 xtal2 5 c14 xtal1 6 c15 avdd 7 c6 v dd c7 lnain 8 rf input y1 c9 l3 mixin- 12 c10 c8 ifin- 15 c12 mixin+ 11 c11 v dd l2 l1 c26 3.0v v dd
choosing standard capacitor values changes c f1 to 470pf and c f2 to 220pf. in the typical application circuit , c f1 and c f2 are named c4 and c3, respective- ly, for ask data, and c21 and c22 for fsk data. data slicers the purpose of a data slicer is to take the analog output of a data filter and convert it to a digital signal. this is achieved by using a comparator and comparing the ana- log input to a threshold voltage. the threshold voltage is set by the voltage on the dsa- pin for the ask receive chain (dsf- for the fsk receive chain), which is connect- ed to the negative input of the data slicer comparator. numerous configurations can be used to generate the data-slicer threshold. for example, the circuit in figure 4 shows a simple method using only one resistor and one capacitor. this configuration averages the analog output of the filter and sets the threshold to approxi- mately 50% of that amplitude. with this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. the sizes of r and c affect how fast the threshold tracks to the analog amplitude. be sure to keep the cor- ner frequency of the rc circuit much lower than the lowest expected data rate. c k khz pf c k khz pf f1 f2 = ()( )()() = ()( )( )( ) 1 000 1 414 100 3 14 5 450 1 414 4 100 3 14 5 225 . .. . . ? ? max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver ______________________________________________________________________________________ 13 table 1. component values for typical application circuit component value for 433.92mhz rf value for 315mhz rf description (%) c3 220pf 220pf 10 c4 470pf 470pf 5 c5 0.047? 0.047? 10 c6 0.1? 0.1? 10 c7 100pf 100pf 5 c8 100pf 100pf 5 c9 1.0pf 2.2pf ?.1pf c10 220pf 220pf 10 c11 100pf 100pf 5 c12 1500pf 1500pf 10 c14 15pf 15pf 5 c15 15pf 15pf 5 c21 220pf 220pf 10 c22 470pf 470pf 5 c23 0.01? 0.01? 10 c26 0.1? 0.1? 10 c27 0.047? 0.047? 10 l1 56nh 100nh coilcraft 0603cs l2 16nh 30nh coilcraft 0603cs l3 10nh 15nh 5 r3 25k ? 25k ? 5 r8 25k ? 25k ? 5 y1 13.2256mhz 9.509mhz crystal y2 10.7mhz ceramic filter 10.7mhz ceramic filter murata sfecv10.7 series note: component values vary depending on pcb layout.
max1471 with this configuration, a long string of nrz zeros or ones can cause the threshold to drift. this configuration works best if a coding scheme, such as manchester coding, which has an equal number of zeros and ones, is used. figure 5 shows a configuration that uses the positive and negative peak detectors to generate the threshold. this configuration sets the threshold to the midpoint between a high output and a low output of the data filter. peak detectors the maximum peak detectors (pdmaxa for ask, pdmaxf for fsk) and minimum peak detectors (pdmi- na for ask, pdminf for fsk), in conjunction with resis- tors and capacitors shown in figure 5, create dc output voltages proportional to the high and low peak values of the filtered ask or fsk demodulated signals. the resistors provide a path for the capacitors to dis- charge, allowing the peak detectors to dynamically fol- low peak changes of the data-filter output voltages. the maximum and minimum peak detectors can be used together to form a data-slicer threshold voltage at a midvalue between the maximum and minimum volt- age levels of the data stream (see the data slicers sec- tion and figure 5). the rc time constant of the peak- detector combining network should be set to at least 5 times the data period. if there is an event that causes a significant change in the magnitude of the baseband signal, such as an agc gain switch or a power-up transient, the peak detectors may ?atch?a false level. if a false peak is detected, the slicing level is incorrect. the max1471 has a fea- ture called peak-detector track enable (trk_en), where the peak-detector outputs can be reset (see figure 6). if trk_en is set (logic 1), both the maximum and minimum peak detectors follow the input signal. when trk_en is cleared (logic 0), the peak detectors revert to their normal operating mode. the trk_en function is automatically enabled for a short time and then disabled whenever the ic recovers from the sleep portion of drx mode, or when an agc gain switch occurs. since the peak detectors exhibit a fast attack/slow decay response, this feature allows for an extremely fast startup or agc recovery. see figure 7 for an illustration of a fast-recovery sequence. in addi- tion to the automatic control of this function, the trk_en bits can be controlled through the serial inter- face (see the serial control interface section). power-supply connections the max1471 can be powered from a 2.4v to 3.6v sup- ply or a 4.5v to 5.5v supply. the device has an on-chip linear regulator that reduces the 5v supply to 3v need- ed to operate the chip. to operate the max1471 from a 3v supply, connect dvdd, avdd, and hvin to the 3v supply. when using a 5v supply, connect the supply to hvin only and con- 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver 14 ______________________________________________________________________________________ figure 3. sallen-key lowpass data filter max1471 dsa+ dsf+ opa+ opf+ dfa dff 100k ? 100k ? c f2 c f1 rssi or fsk demod table 2. coefficients to calculate c f1 and c f2 filter type a b butterworth (q = 0.707) 1.414 1.000 bessel (q = 0.577) 1.3617 0.618 figure 4. generating data-slicer threshold using a lowpass filter max1471 data slicer adata fdata dsa- dsf- dsa+ dsf+ c r
nect avdd and dvdd together. in both cases, bypass dvdd and hvin with a 0.01? capacitor and avdd with a 0.1? capacitor. place all bypass capacitors as close as possible to the respective supply pin. max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver ______________________________________________________________________________________ 15 figure 5. generating data-slicer threshold using the peak detectors maximum peak detector max1471 data slicer pdmaxa pdmaxf adata fdata c minimum peak detector pdmina pdminf r r c figure 6. peak-detector track enable trk_en = 1 minimum peak detector pdmina pdminf trk_en = 1 maximum peak detector baseband filter pdmaxa pdmaxf max1471 to slicer input
max1471 serial control interface communication protocol the max1471 can use a 4-wire interface or a 3-wire interface (default). in both cases, the data input must follow the timing diagrams shown in figures 8 and 9. note that the dio line must be held low while cs is high. this is to prevent the max1471 from entering dis- continuous receive mode if the drx bit is high. the data is latched on the rising edge of sclk, and there- fore must be stable before that edge. the data sequencing is msb first, the command (c[3:0]; see table 3), the register address (a[3:0]; see table 4) and the data (d[7:0]; see table 5). the mode of operation (3-wire or 4-wire interface) is selected by dout_fsk and/or dout_ask bits in the configuration register. either of those bits selects the askout and/or fskout line as a serial data output. upon receiving a read register command (0x2), the serial interface outputs the data on either pin, accord- ing to figure 10. if neither of these bits are 1, the 3-wire interface is selected (default on power-up) and the dio line is effectively a bidirectional input/output line. dio is selected as an output of the max1471 for the following cs cycle whenever a read command is received. the cpu must tri-state the dio line on the cycle of cs that follows a read command, so the max1471 can drive the data output line. figure 11 shows the diagram of the 3-wire interface. note that the user can choose to send either 16 cycles of sclk, as in the case of the 4- wire interface, or just eight cycles, as all the registers are 8-bits wide. the user must drive dio low at the end of the read sequence. the master reset command (0x3) (see table 3) sends a reset signal to all the internal registers of the max1471 just like a power-off and power-on sequence would do. the reset signal remains active for as long as cs is high after the command is sent. continuous receive mode (drx = 0) in continuous receive mode, individual analog modules can be powered on directly through the power configu- ration register (register 0x0). the sleep bit (bit 0) overrides the power settings of the remaining bits and puts the part into deep-sleep mode when set. it is also necessary to write the frequency divisor of the external crystal in the oscillator frequency register (register 0x3) to optimize image rejection and to enable accurate cali- bration sequences for the polling timer and the fsk demodulator. this number is the integer result of f xtal /100khz. if the fsk receive function is selected, it is necessary to perform an fsk calibration to improve receive sensitivi- ty. polling timer calibration is not necessary. see the calibration section for more information. 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver 16 ______________________________________________________________________________________ figure 7. fast receiver recovery in fsk mode utilizing peak detectors 200mv/div data output 2v/div min peak detector max peak detector receiver enabled, trk_en set trk_en cleared filter output data output 100 s/div figure 8. digital communications timing diagram t dh high-impedance data out data in high-impedance hi-z sclk dio d7 d0 cs t css t ch t di t sc t cl t dv t csh t do t tr t cs t csi
discontinuous receive mode (drx = 1) in the discontinuous receive mode (drx = 1), the power signals of the different modules of the max1471 toggle between off and on, according to internal timers t off , t cpu , and t rf . it is also necessary to write the frequency divisor of the external crystal in the oscil- lator frequency register (register 0x3). this number is the integer result of f xtal /100khz. before entering the discontinuous receive mode for the first time, it is also necessary to calibrate the timers (see the calibration section). the max1471 uses a series of internal timers (t off , t cpu , and t rf ) to control its power-up. the timer sequence begins when both cs and dio are one. the max1471 has an internal pullup on the dio pin, so the user must tri-state the dio line when cs goes high. the external cpu can then go to a sleep mode during t off . a high-to-low transition on dio, or a low level on dio serves as the wake-up signal for the cpu, which must then start its wake-up procedure, and drive dio low before t low expires (t cpu + t rf ). once t rf expires, the max1471 enables the fskout and/or askout data outputs. the cpu must then keep dio low for as long as it may need to analyze any received data. releasing dio causes the max1471 to pull up dio, reinitiating the t off timer. oscillator frequency register (address: 0x3) the max1471 has an internal frequency divider that divides down the crystal frequency to 100khz. the max1471 uses the 100khz clock signal when calibrating itself and also to set the image-rejection frequency. the hexadecimal value written to the oscillator frequency reg- ister is the nearest integer result of f xtal /100khz. max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver ______________________________________________________________________________________ 17 figure 9. data input diagram sclk a2 a1 d0 address data dio c3 a3 c0 c1 c2 a0 d7 d6 d5 d4 d3 d2 d1 command cs figure 10. read command on a 4-wire serial interface sclk cs 0 0 1 0 0 0 0 0 0 0 0 0 a3 a2 a1 a0 dio c3 c2 c1 c0 a3 a2 a1 a0 d0 d7 command address data read command address data adata (if dout_ask = 1) r7 r6 r5 r4 r3 r2 r1 r0 r0 r7 register data register data fdata (if dout_fsk = 1) r7 r6 r5 r4 r3 r2 r1 r0 r0 r7 register data register data
max1471 for example, if data is being received at 315mhz, the crystal frequency is 9.509375mhz. dividing the crystal frequency by 100khz and rounding to the nearest inte- ger gives 95, or 0x5f hex. so for 315mhz, 0x5f would be written to the oscillator frequency register. agc dwell timer register (address: 0xa) the agc dwell timer holds the agc in low-gain state for a set amount of time after the power level drops below the agc switching threshold. after that set amount of time, if the power level is still below the agc threshold, the lna goes into high-gain state. this is important for ask since the modulated data may have a high level above the threshold and a low level below the threshold, which without the dwell timer would cause the agc to switch on every bit. the agc dwell time is dependent on the crystal fre- quency and the bit settings of the agc dwell timer reg- ister. to calculate the dwell time, use the following equation: where reg 0xa is the value of register 0xa in decimal. to calculate the value to write to register 0xa, use the following equation and use the next integer higher than the calculated result: reg 0xa 3.3 x log 10 (dwell time x f xtal ) for manchester code (50% duty cycle), set the dwell time to at least twice the bit period. for nonreturn-to- zero (nrz) data, set the dwell to greater than the peri- od of the longest string of zeros or ones. for example, using manchester code at 315mhz (f xtal = 9.509375mhz) with a data rate of 4kbps (bit period = 125?), the dwell time needs to be greater than 250?: reg 0xa 3.3 x log 10 (250? x 9.509375mhz) 11.14 choose the register value to be the next integer value higher than 11.14, which is 12 or 0x0c hex. the default value of the agc dwell timer on power-up or reset is 0x0d. d f well time reg0xa xtal = 2 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver 18 ______________________________________________________________________________________ figure 11. read command in 3-wire interface 0 0 1 0 0 0 0 0 0 0 0 0 a3 a2 a1 a0 read command address data dio r7 r6 r5 r4 r3 r2 r1 r0 r0 r7 register data register data 16 bits of data cs sclk 0 0 1 0 0 0 0 0 0 0 0 0 a3 a2 a1 a0 r7 r6 r5 r4 r3 r2 r1 a3 8 bits of data read command address data register data dio cs sclk table 3. command bits c[3:0] description 0x0 no operation 0x1 write data 0x2 read data 0x3 master reset 0x4?xf not used
calibration the max1471 must be calibrated to ensure accurate timing of the off timer in discontinuous receive mode or when receiving fsk signals. the first step in calibration is ensuring that the oscillator frequency register (address: 0x3) has been programmed with the correct divisor value (see the oscillator frequency register section). next, enable the mixer to turn the crystal dri- ver on. calibrate the polling timer by setting pol_cal_en = 1 in the configuration register (register 0x1). upon com- pletion, the pol_cal_done bit in the status register (register 0x8) is 1, and the pol_cal_en bit is reset to zero. if using the max1471 in continuous receive mode, polling timer calibration is not needed. fsk receiver calibration is a two-step process. set fskcallsb = 1 (register 0x1) or to reduce the calibra- tion time, accuracy can be sacrificed by setting the fskcallsb = 0. next, initiate fsk receiver calibration, set fsk_cal_en = 1. upon completion, the fsk_cal_done bit in the status register (register 0x8) is one, and the fsk_cal_en bit is reset to zero. when in continuous receive mode and receiving fsk data, recalibrate the fsk receiver after a significant change in temperature or supply voltage. when in dis- continuous receive mode, the polling timer and fsk receiver (if enabled) are automatically calibrated during every wake-up cycle. off timer (t off ) the first timer, t off (see figure 12), is a 16-bit timer that is configured using: register 0x4 for the upper byte, register 0x5 for the lower byte, and bits prescale1 and prescale0 in the configuration register (register 0x1). table 10 summarizes the configuration of the t off timer. the prescale1 and prescale2 bits set the size of the shortest time possible (t off time base). the data written to the t off registers (0x4 and 0x5) is multi- plied by the time base to give the total t off time. on power-up, the off timer registers are set to zero and must be written before using drx mode. max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver ______________________________________________________________________________________ 19 table 4. register summary register a[3:0] register name description 0x0 power configuration enables/disables the lna, agc, mixer, baseband, peak detectors, and sleep mode (see table 6). 0x1 configuration sets options for the device such as output enables, off-timer prescale, and discontinuous receive mode (see table 7). 0x2 control controls agc lock, peak-detector tracking, as well as polling timer and fsk calibration (see table 8). 0x3 oscillator frequency sets the internal clock frequency divisor. this register must be set to the integer result of f xtal /100khz (see the oscillator frequency register section). 0x4 off timer? off (upper byte) 0x5 off timer? off (lower byte) sets the duration that the max1471 remains in low-power mode when drx is active (see table 10). 0x6 cpu recovery timer? cpu increases maximum time the max1471 stays in lower power mode while cpu wakes up when drx is active (see table 11). 0x7 rf settle timer? rf (upper byte) 0x8 rf settle timer? rf (lower byte) during the time set by the settle timer, the max1471 is powered on with the peak detectors and the data outputs disabled to allow time for the rf section to settle. dio must be driven low at any time during t low = t cpu + t rf or the timer sequence restarts (see table 12). 0x9 status register (read only) provides status for pll lock, agc state, crystal operation, polling timer, and fsk calibration (see table 9). 0xa agc dwell timer controls the dwell (release) time of the agc.
max1471 during t off , the max1471 is operating with very low supply current (5.0? typ), where all of its modules are turned off, except for the t off timer itself. upon com- pletion of the t off time, the max1471 signals the user by asserting dio low. cpu recovery timer (t cpu ) the second timer, t cpu (see figure 12), is used to delay the power-up of the max1471, thereby providing extra power savings and giving a cpu the time required to complete its own power-on sequence. the cpu is sig- naled to begin powering up when the dio line is pulled low by the max1471 at the end of t off . t cpu then begins counting down, while dio is held low by the max1471. at the end of t cpu , the t rf counter begins. t cpu is an 8-bit timer, configured through register 0x6. the possible t cpu settings are summarized in table 11. the data written to the t cpu register (0x6) is multiplied by 120? to give the total t cpu time. on power-up, the cpu timer register is set to zero and must be written before using drx mode. rf settle timer (t rf ) the third timer, t rf (see figure 12), is used to allow the rf sections of the max1471 to power up and stabilize before ask or fsk data is received. t rf begins count- 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver 20 ______________________________________________________________________________________ table 5. register configuration address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 power configuration (0x0) 0 0 0 0 lna_en agc_en mixer_ en fskbb_ en fskpd_ en askbb_ en askpd_ en sleep configuration (0x1) 0 0 0 1 x gain set* fskcall sb fsk_ dout ask_ dout toff_ ps1 toff_ ps0 drx_ mode control (0x2) 0 0 1 0 x agc lock xx fsktrk_ en asktrk_ en p ol_ c al_e n fsk_cal _en oscillator frequency (0x3) 0 0 1 1 d7d6d5d4d3d2d1d0 off timer (upper byte) (0x4) 0 1 0 0 t15 t14 t13 t12 t11 t10 t9 t8 off timer (lower byte) (0x5) 0 1 0 1 t7t6t5t4t3t2t1t0 cpu recovery timer (0x6) 0 1 1 0 t7t6t5t4t3t2t1t0 rf settle timer (upper byte) (0x7) 0 1 1 1 t15 t14 t13 t12 t11 t10 t9 t8 rf settle timer (lower byte) (0x8) 1 0 0 0 t7t6t5t4t3t2t1t0 status register (read only) (0x9) 1 0 0 1 lock det agcst clk alive xxx p ol_c al _d o n e fsk_cal _done agc dwell timer (0xa) 1 0 1 0 x x x dt4 dt3* dt2* dt1 dt0* * power-up state = 1. all other bits, power-up state = 0.
ing once t cpu has expired. at the beginning of t rf , the modules selected in the power control register (register 0x0) are powered up with the exception of the peak detectors and have the t rf period to settle. at the end of t rf , the max1471 stops driving dio low and enables adata, fdata, and peak detectors if chosen to be active in the power configuration register (0x0). the cpu must be awake at this point, and must hold dio low for the max1471 to remain in operation. the cpu must begin driving dio low any time during t low = t cpu + t rf . if the cpu fails to drive dio low, dio is pulled high through the internal pullup resistor, and the timer sequence is restarted, leaving the max1471 powered down. any time the dio line is dri- ven high while the drx = 1, the drx sequence is initi- ated, as defined in figure 12. t rf is a 16-bit timer, configured through registers 0x7 (upper byte) and 0x8 (lower byte). the possible t rf set- tings are in table 12. the data written to the t rf register (0x7 and 0x8) is multiplied by 120? to give the total t rf time. on power-up, the rf timer registers are set to zero and must be written before using drx mode. typical power-up procedure here is a typical power-up procedure for receiving either ask or fsk signals at 315mhz in continuous mode: 1) write 0x3000 to reset the part. 2) write 0x10fe to enable all rf and baseband sections. 3) write 0x135f to set the oscillator frequency register to work with a 315mhz crystal. 4) write 0x1120 to set fskcallsb for an accurate fsk calibration. 5) write 0x1201 to begin fsk calibration. 6) read 0x2900 and verify that bit 0 is 1 to indicate fsk calibration is done. the max1471 is now ready to receive ask or fsk data. due to the high sensitivity of the receiver, it is recom- mended that the configuration registers be changed only when not receiving data. receiver desensitization may occur, especially if odd-order harmonics of the sclk line fall within the if bandwidth. max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver ______________________________________________________________________________________ 21 table 6. power configuration register (address: 0x0) bit id bit name bit location (0 = lsb) power-up state function lna_en lna enable 7 0 1 = enable lna 0 = disable lna agc_en agc enable 6 0 1 = enable agc 0 = disable agc mixer_en mixer enable 5 0 1 = enable mixer 0 = disable mixer fskbb_en fsk baseband enable 40 1 = enable fsk baseband 0 = disable fsk baseband fskpd_en fsk peak detector enable 30 1 = enable fsk peak detectors 0 = disable fsk peak detectors askbb_en ask baseband enable 20 1 = enable ask baseband 0 = disable ask baseband askpd_en ask peak detector enable 10 1 = enable ask peak detectors 0 = disable ask peak detectors sleep sleep mode 0 0 1 = deep-sleep mode 0 = normal operation
max1471 layout considerations a properly designed pcb is an essential part of any rf/microwave circuit. on high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radia- tion. at high frequencies, trace lengths that are on the order of /10 or longer act as antennas. keeping the traces short also reduces parasitic induc- tance. generally, 1in of a pcb trace adds about 20nh of parasitic inductance. the parasitic inductance can have a dramatic effect on the effective inductance of a passive component. for example, a 0.5in trace con- necting a 100nh inductor adds an extra 10nh of induc- tance or 10%. to reduce the parasitic inductance, use wider traces and a solid ground or power lane below the signal traces. also, use low-inductance connections to ground on all gnd pins, and place decoupling capacitors close to all v dd or hvin connections. 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver 22 ______________________________________________________________________________________ table 7. configuration register (address: 0x1) bit id bit name bit location (0 = lsb) power-up state function x don? care 7 0 don? care. gainset gain set 6 1 0 = lna low-gain state. 1 = lna high-gain state. for manual gain control, enable the agc (agc_en = 1), set lna gain state to desired setting, then disable the agc (agc_en = 0). fskcallsb fsk accurate calibration 50 fskcallsb = 1 enables a longer, more accurate fsk calibration. fskcallsb = 0 provides for a quick, less accurate fsk calibration. dout_fsk fskout enable 4 0 this bit enables the fdata pin to act as the serial data output in 4-wire mode. (see the communication protocol section.) dout_ask askout enable 3 0 this bit enables the adata pin to act as the serial data output in 4-wire mode. (see the communication protocol section.) toff_ps1 off-timer prescale 2 0 toff_ps0 off-timer prescale 1 0 sets lsb size for the off timer. (see the off timer section.) drx_mode receive mode 0 0 1 = discontinuous receive mode. (see the discontinuous receive mode section.) 0 = continuous receive mode. (see the continuous receive mode section.)
max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver ______________________________________________________________________________________ 23 table 8. control register (address: 0x2) bit id bit name bit location (0 = lsb) power-up state function x none 7 don? care don? care. agclock agc lock 6 0 locks the lna gain in its present state. x none 5, 4 don? care. fsktrk_en fsk peak detector track enable 30 enables the tracking mode of the fsk peak detectors when fsktrk_en = 1. (see the peak detector s section.) asktrk_en ask peak detector track enable 20 enables the tracking mode of the ask peak detectors when asktrk_en = 1. (see the peak detectors section.) pol_cal_en polling timer calibration enable 10 pol_cal_en = 1 starts the polling timer calibration. calibration of the polling timer is needed when using the max1471 in discontinous receive mode. pol_cal_en resets when calibration completes properly. (see the calibration section.) fsk_cal_en fsk calibration enable 00 fsk_cal_en starts the fsk receiver calibration. fsk_cal_en resets when calibration completes properly. (see the calibration section.) table 9. status register (read only) (address: 0x9) bit id bit name bit location (0 = lsb) function lockdet lock detect 7 0 = internal pll is not locked so the max1471 will not receive data. 1 = internal pll is locked. agcst agc state 6 0 = lna in low-gain state. 1 = lna in high-gain state. clkalive clock/crystal alive 5 0 = no valid clock signal seen at the crystal inputs. 1 = valid clock at crystal inputs. x none 4, 3, 2 don? care. pol_cal_done polling timer calibration done 1 0 = polling timer calibraton in progress or not completed. 1 = polling timer calibration is complete. fsk_cal_done fsk calibration done 0 0 = fsk calibration in progress or not completed. 1 = fsk calibration is compete.
max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver 24 ______________________________________________________________________________________ figure 12. drx mode sequence of the max1471 adata or fdata t off t off dio t cpu t rf cs t cpu t low t rf table 12. rf settle timer (t rf ) configuration time base (1 lsb) min t rf reg 0x7 = 0x00 reg 0x8 = 0x01 max t rf reg 0x7 = 0xff reg 0x8 = 0xff 120? 120? 7.86s table 10. off-timer (t off ) configuration prescale1 prescale0 t off time base (1 lsb) min t off reg 0x4 = 0x00 reg 0x5 = 0x01 max t off reg 0x4 = 0xff reg 0x5 = 0xff 0 0 120? 120? 7.86s 0 1 480? 480? 31.46s 1 0 1920? 1.92ms 2 min 6s 1 1 7680? 7.68ms 8 min 23s table 11. cpu recovery timer (t cpu ) configuration time base (1 lsb) min t cpu reg 0x6 = 0x01 max t cpu reg 0x6 = 0xff 120? 120? 30.72ms
max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver ______________________________________________________________________________________ 25 chip information process: cmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 32 tqfn-ep t3255+3 21-0140 90-0001
max1471 315mhz/434mhz low-power, 3v/5v ask/fsk superheterodyne receiver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 2 11/10 updated ordering information , absolute maximum ratings , ac electrical characteristics, and package information 1, 2, 4, 25 3 12/10 updated ordering information and ac electrical characteristics 1, 3

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